Graph accelerators have emerged as a promising solution for processing large-scale sparse graphs, leveraging the in-situ compu-tation of ReRAM-based crossbars to maximize computational efficiency. However, existing designs suffer from memristor access overhead due to the large number of graph partitions. This leads to increased execution time, higher energy consumption, and re-duced circuit lifetime. This paper proposes a graph processing method that minimizes memristor write operations by identifying frequent subgraph patterns and assigning them to graph engines, referred to as static, allowing most subgraphs to be processed without a need for crossbar reconfiguration. Experimental results show speed up to 2.38× speedup and 7.23× energy savings com-pared to state-of-the-art accelerators. Furthermore, our method extends the circuit lifetime by 2× compared to state-of-the-art ReRAM graph accelerators.
@inproceedings{DATE2026,title={Leveraging Recurrent Patterns in Graph Accelerators},author={Rahimi, Masoud and Beux, Sébastien Le},booktitle={Design, Automation and Test in Europe Conference},year={2026},month=apr,}
2016
Design and Implementation of High-Speed SPI protocol in FPGA
@mastersthesis{CitekeyMastersthesis,title={Design and Implementation of High-Speed SPI protocol in FPGA},author={Rahimi, Masoud},school={Shahid Beheshti University},address={Tehran, Iran},year={2016},month=jan}
2015
Design and Implementation of SPI Display Controller Interface on FPGA
Rahimi, Masoud, and Eshghi, Mohammad
In International Conference on New Research Findings in Electrical Engineering and Computer Science Aug 2015
Serial Peripheral Interface is one of the most commonly used serial communication protocols in embedded systems and short-distance communications between peripherals of a system or a chip. SPI makes communication simple and can be used for high-speed peripherals. This paper represents the design and implementation of the SPI protocol on FPGA. We have designed Master mode, Slave mode, and display controller interface separately. We have simplified the protocol to gain high speed and less area utilization compared to previous works and have kept the main features of SPI. We have used Motorola’s latest SPI block guide to gain higher compatibility with other systems. The SPI is designed using VHDL tools and is synthesized on Xilinx’s SPARTAN6 FPGA.
@inproceedings{COMCONF01_217,title={Design and Implementation of SPI Display Controller Interface on FPGA},author={Rahimi, Masoud and Eshghi, Mohammad},booktitle={International Conference on New Research Findings in Electrical Engineering and Computer Science},year={2015},month=aug}
A Simple Constant Transconductance Bias Circuit for CMOS Analog Integrated-Circuits
Rahimi, Masoud, and Hasandzadeh, Alireza
In International Conference on Electrical Engineering May 2015
This paper represents a simple way of design and simulation a constant transconductance biasing circuit. We used a variable on-chip resistor instead of an off-chip resistor. A MOSFET biased in the triode region can be used as a variable resistor. The transconductance generated by this circuit has been designed with a 180nm CMOS technology process and a 3V power supply voltage. This design shows less than 8% variation of transconductance with up to 20% changes in power supply voltage and less than 1% variation of transconductance with 60°C of temperature changes.
@inproceedings{ICEE2015,title={A Simple Constant Transconductance Bias Circuit for CMOS Analog Integrated-Circuits},author={Rahimi, Masoud and Hasandzadeh, Alireza},booktitle={International Conference on Electrical Engineering},year={2015},month=may}